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1/14 sta020 april 2010 ? monolithic digital audio interface transmitter ? 3.3v supply voltage ? supports: ? aes/ebu, iec 958, ? s/pdif, & eiaj cp-340 ? professional and consumer formats ? parity bits and crc codes generated ? transparent mode allows direct connection of sta020d and sta120 description the sta020d is a monolit hic cmos device which encodes and transmits audio data according to the aes/ebu, iec 958, s/pdif, & eiaj cp-340 inter- face standards. it suppor ts 96khz sample rate op- eration the sta020d accepts audio and digital data which is then multiplexed, encoded and driven onto a cable. the audio serial port is double buffered and capa- ble of supporting a wide variety of formats. the sta020d multiplexes the channel, user, and validity data directly from serial input pins with dedicated input pins for the most important chan- nel status bits. so24 ordering number: sta020d 96khz digital audio interface transmitter block diagram audio serial port registers mux differential m0 m1 m2 mck rst sck fsync sdata c u v dedicated channel status bus cbl trnpt 7 txn txp 20 17 16 5 6 7 8 21 22 23 10 11 9 15 24 d97au599a vd+ 19 gnd 18 obsolete product(s) - obsolete product(s)
sta020 2/14 absolute maximum ratings recommended operating conditions (gnd = 0v; all voltages with respect to ground) pin connections (top view) symbol parameter value unit v d+ dc power supply 4 v v ind digital input voltage -0.3 to v d+ 0.3 v t amb ambient operating temperature (power applied) -20 to +85 c t stg storage temperature -40 to 150 c symbol parameter test condition min. typ. max. unit v d+ dc voltage 3 3.3 3.6 v t amb ambient operating temp. 0 25 70 c pin description n pin function power supply connections 18 gnd ground. 19 vd+ positive digital power. nominally +3.3v. audio input interface 6 sck serial clock. serial clock for sdata pin which can be configured (via the m0, m1 and m2 pins) as an input or output and can sample data on the rising or falling edge.a s an output, sck will contain 32 clocks for every audio sample. sck fsync sdata v c/sbf c9/c15 u 1 3 2 4 5 6 7 8 9 em1/c8 cbl/sbc em0/c9 rst txn gnd vd+ 19 18 17 16 15 13 14 d97au608a 10 11 12 24 23 22 21 20 c7/c3 pro c1/fc0 c6/c2 mck txp m2 m1 m0 trnpt/fc1 obsolete product(s) - obsolete product(s)
3/14 sta020 7 fsync frame sync. delineates the serial data and may indicate t he particular channel, left or right and may be an input or output. the format is based on m0, m1 and m2 pins. 8 sdata serial data. audio data serial input pin. 21, 22,23 m0, m1, m2 serial port mode select. selects the format of fsync and the sample edge of sck with respect to sdata. control pins 1c7 /c3 channel status bit 7/channel status bit 3 in professional mode, c7 is the inverse of channel status bit 7. in consumer mode, c3 is the inverse of channel status bit 3, c7 /c3 are ignored in transparent mode. 2pro professional/consumer select. selects between professional mode (pro low) and consumer mode (pro high). this pin defines the functionality of the channel status parallel pins. pro is ignored in transparent mode. 3c1 /fc0 channel status bit 1/frequency control 0. in professional mode, c1 is the inverse of c hannel status bit 1. in consumer mode, fc0 and fc1 are encoded versions of channel status bi ts 24 and 25 (bits 0 and 1 of byte 3). when fc0 and fc1 are both high, cd mode is sele cted. c1/fc0 are ignored in transparent mode. 4c6 /c2 channel status bit 6/channel status bit 2. in professional mode, c6 is the inverse of channel status bit 6. in consumer mode, c2 is the inverse of channel status bit 2. c6 /c2 are ignored in transparent mode 9vvalidity. validity bit serial input port. this bit is defined as per the digital audio standards wherein v = 0 signifies the audio signal is suitable for co nversion to analog. v = 1 signifies the audio signal is not suitable for conv ersion to analog, i.e. invalid. 10 c/sbf channel status serial input/subcode frame clock. in professional and consumer modes this pin is the channel status serial input port. in cd mode this pin inputs the cd subcode frame clock. 11 u user bit. user bit serial input port. 12 c9 /c15 channel status bit 9/channel status bit 15. in professional mode, c9 is the inverse of channel status bi t 9 (bit 1 of byte 1). in consumer mode, c15 is the inverse of channel status bit 15 (bit 7 of byte 1). c9 /c15 are ignored in transparent mode. 13 em1/c8 emphasis 1/channel status bit 8. in professional mode, em0 and em1 encode channel status bits 2, 3 and 4. in consumer mode, c8 is the inverse of channel status bit 8 (bit 0 of byte 1). em1/c8 are ignored in transparent mode. 14 em0/c9 emphasis 0/channel status bit 9. in professional mode, em0 and em1 encode channel status bits 2, 3 and 4. in consumer mode, c9 is the inverse of channel status bit 9 (bit 1 of byte 1). em0/c9 are ignored in transparent mode. 15 cbl/sbc channel status block output/subcode bit clock. in professional and consumer modes, the channel status block output is high for the first 15 bytes of channel status. in cd mode, this pin outputs the subcode bit clock. 16 rst master reset. when low, all internal counters are reset. pin description (continued) n pin function obsolete product(s) - obsolete product(s)
sta020 4/14 digital characteristics (t amb = 25c; v d+ = 3.3v 10%) note 1 : mck must be 128x the input word rate, except in transparent mode where mck is 256x the input word rate. figure 1. sta020d professional & consumer modes typical connection diagram. 24 trnpt/fc1 transparent mode/frequency control 1. in professional mode, setting trnpt low selects normal operation & cbl is an output. setting trnpt high, allows the sta020d to be connected directly to an sta120. in transparent mode, cbl is an input & mck must be at 256 fs. in consumer mode, fc0 and fc1 are encoded versions of channel status bits 24 and 25. when fc0 and fc1 are both high, cd mode is selected. transmitter interface 5 mck master clock. clock input at 128x the sample frequency whic h defines the transmit timing. in trasparent mode mck must be 256 fs. 20, 17 txp, txn differential line drivers. symbol parameter test condition min. typ. max. unit v ih high-level input voltage 2.0 v dd +0.3 v v il low-level input voltage -0.3 +0.8 v v oh high-level output voltage i o = 200 a v dd -1.0 v v ol low-level output voltage i o = 3.2ma 0.4 v i in input leakage current 1.0 10 a mck master clock frequency (note 1) 26 mhz master clock duty cycle (high time/cycle time) 40 60 % pin description (continued) n pin function 7 6 8 15 10 audio data processor controller or unused channel status bits control 11 9 rst 16 v u c cbl sdata sck fsync 8 dedicated c.s. bits external clock 5 mck sta020 +3.3v 19 vd+ gnd trnpt 24 18 0.1 f serial port mode select transmitter circuit m0 23 m1 22 m2 21 txp 20 txn 17 d97au600a obsolete product(s) - obsolete product(s)
5/14 sta020 figure 2. sta020d typical connection diagram. general description the sta020d is a monolithic cmos circuit that enc odes and transmits audio and digital data according to the aes/ebu, iec 958, s/pdif, and eiaj cp-340 interfac e standards. the chip accepts audi o and con- trol data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through a transformer, to a transmission line. the sta020d has dedicated pins for the most important control bits and a serial input port for the c, u and v bits. line drivers the differential line drivers for sta020d are low skew , low impedance, differential outputs capable of driv- ing 110ohm transmission lines. (rs422 line driver compatible). they can also be disabled by resetting the device (rst = low). sta020d description the sta020d accepts 16 to 24-bit audio samples through a serial port configured in one of seven formats; provides several pins dedicated to particular channe l status bits and allows all channel status, user and validity bits to be serially input through port pins. th is data is multiplexed, the parity bit is generated and the bit stream is biphase-mark encoded and driven through an rs422 line driver. the sta020d operates as a professi onal or consumer interface tran smitter selectable by pin 2, pro . as a professional interface device, the dedicated channel status input pins are defined according to the pro- fessional standard, and the crc code (c.s. byte 23) can be internally generated. as a consumer device, the dedicated channel status input pins are defined according to the consumer standard. a submode provided under the consumer m ode is compact disk, cd, mode. when transmitting data from a compact disk, the cd subcode port can accept cd subcode data, extract channel status in- 7 6 8 15 10 audio data processor reset control 11 9 rst 16 v u sbf sbc sdata sck fsync 8 dedicated c.s. bits external clock 5 mck sta020 +5v 19 vd+ gnd 18 0.1 f serial port mode select transmitter circuit m0 23 m1 22 m2 21 txp 20 txn 17 d99au989a decoder subcode port channel status bits control obsolete product(s) - obsolete product(s)
sta020 6/14 formation from it, and transmit it as user data. the master clock , mck, controls timing for the entire chip and must be 128xfs. as an example, if stereo data is input to the sta020d at 44.1khz, mck input must be 128 times that or 5.6448mhz. audio serial port the audio serial port is used to enter audio data and consists of three pi ns: sck, sdata and fsync, sck clocks in sdata, which is do uble buffered, while fsync delineates the audio samples and may in- dicate the particular channel, left or right. to support many different interfaces, m2, m1 and m0 select one of seven different formats for the serial port. the coding is shown in table 3 while the formats are shown in figure 3. format 0 and 1 are designed to interface with crystal adcs. format 2 communicates with motorola and ti dsps. format 3 is reserved. format 4 is compatible with the i2s standard. formats 5 and 6 make the sta020d look similar to existing 16- and 18-bit dacs and interpolation filters. format 7 is an msb-last format and is conducive to serial arithmetic. sck and fsync are outputs in format 0 and inputs in all other formats. in format 2, the rising edge of fsync delineates samp les and the falling edge must occur a minimum of one bit period before or after the rising edge. in all formats except 2, fsync contains left/ right information requiring both edges of fsync to delineate samples. formats 5 and 6 require a minimum of 16- or 18-bit audio words respectively. in all formats other than 5 and 6, the sta020d can accept any word length from 16 to 24 bits by adding leading ze ros in format 7 and trailing zeros in the other formats, or by restricting the number of sck periods between active edges of fsync to the sample word length. fsync must be derived from mck, either through a dsp using the same clock or using counters. if sfync moves (jitters) with respect to mck by four mck periods, the internal counters and cbl may be reset. table 1. audio port modes m2 m1 m0 format 0 0 0 0 - fsync & sck output 0 0 1 1 - left/right, 16-24 bits 0 1 0 2 - word sync, 16-24 bits 0113 - reserved 100 4 - left/right, i 2 s compatible 1 0 1 5 - lsb justified, 16 bits 1 1 0 6 - lsb justified, 18 bits 1 1 1 7 - msb last, 16-24 bits obsolete product(s) - obsolete product(s)
7/14 sta020 figure 3. audio serial port formats. c, u, v serial port the serial input pins for channel status (c), user (u), and validity (v) are sampled during the first bit period after the active edge of fsync for all formats except format 4. format 4 is sampled during the second bit period (coincident with the msb). in figure 3, th e arrows on sck indicate when the c, u, and v bits are sampled. the c, u, and v bits are transmitted with the audio sample entered before fsync edge that sampled it. the v bit, as defined in the audio standards, is set to zero to indicate the audio data is suitable for conversion to analog. therefore, when the audio da ta is errored, or the data is not audio, the v bit should be set high. the channel status serial input pin (c) is not available in consumer mode when the cd subcode port is enabled (fc1 = fc0 = high). any channel status data entered through the channel status serial input (c) is logically or?ed with the data entered through the dedicated pins or internally gen- erated. fsync(out) msb lsb msb lsb msb left right sck(out) sdata(in) fsync(in) msb lsb msb lsb msb left right sck(in) sdata(in) fsync(in) msb lsb msb lsb msb left right sck(in) sdata(in) format 0: format 1: format 2: (reserved) fsync(in) msb lsb msb lsb msb left right sck(in) sdata(in) fsync(in) lsb msb lsb sck(in) sdata(in) format 3: format 4: format 5: left right lsb msb 16 bits 16 bits fsync(in) lsb msb lsb sck(in) sdata(in) format 6: left right lsb msb 18 bits 18 bits fsync(in) msb lsb msb sck(in) sdata(in) format 7: left right msb lsb d97au604 obsolete product(s) - obsolete product(s)
sta020 8/14 rst and cbl (trnpt is low) when rst goes low, the differential line drivers are set to ground. in order to properly synchronize the st020 to the audio serial port, the transmit timing counters, which include cbl, are not enabled after rst goes high until eight and one half sck periods after reset is exited) of fsync. when fsync is configured as a left/right signal (all defined formats except 2), the counters and cbl are not enabled until the right sample is being transmitted). this guarantees that channel a is left and channel b is right as per the digital audio interface specs. as shown in figure 4, channel block start output (cbl), can assist in serially inputting the c, u and v bits as cbl goes high one bit period before the first bit of the preamble of the first sub-frame of the channel status block is transmitted. this sub-frame contains channel status byte 0, bit 0. cbl returns low one bit period before the start of the frame that contains bit 0 of channel status byte 16. cbl is not available when the cd subcode port is enabled. figure 4 illustrates timing fo r stereo data input on th e audio port. notice how cbl rises while the right channel data (right 0) is input, but the previous left channel (left 0) is being transmitted as the first sub- frame of the channel status block (starting with preamb le z). the c, u, and v input ports only need to be valid for a short period after fsync changes. a sub-frame includes one audio sample while a frame in- cludes a stereo pair. a channel status (c.s.) block contains 24 bytes of channel status and 384 audio sam- ples (or 192 stereo pairs, or frames, of samples). figure 4 shows the cuv ports as having left and right bits (e.g. cuv0l, cuv0r). since the c.s. block is defin ed as 192 bits, or one bit per frame, there are ac- tually 2 c.s. blocks, one for channel a (left) and one for channel b (right). when inputting stereo audio data, both blocks normally contain the same information, so c0l and c0r from the input port pin are both channel status bit 0 of byte 0, which is defined as professional/consumer. these first two bits from the port, c0l and c0r, are logically or?ed with the inverse pro , since pro is a dedicated channel status pin defined as c.s. bit 0. also, if in professional mode, c1 , c6 , c7 and c9 are dedicated c.s. pins. the inverse of c1 is logically or?ed with channel status input ports bits c1l and c1r. in similar fashion, c6 , c7 and c9 are or?ed with their respective input bits. also, the c bits in cu v128l and cuv128r are both channel status block bit 128, which is bit 0 of channel status byte 16. figure 4. cbl and transmitter timing. cuv0l cuv191r cuv0r cuv0l cuv1l cuv0r cuv1r cuv1l cuv128r cuv128l cuv0l cuv191r cuv0r cuv0l left 0 right 0 left 1 left 128 right 128 left 0 right 0 c bits from cpin c bits or'ed w/pro pin c bits or'ed w/c1 pin bits 0 of c.s. block byte 16 right 191 left 0 right 0 left 128 right 128 preamble y vucp191r preamble z vucp0l preamble y vucp0r vucp127r preamble x vucp128l preamble y preamble z aux data lsb left 0 - audio data msb v0 u0 c0 p0 28 29 30 31 27 8 37 4 0 sub-frame bit d99au990 sdata trnpt high cbl trnpt low fsync c,u,v trnpt high trnpt low txp txn obsolete product(s) - obsolete product(s)
9/14 sta020 transparent mode in certain applications it is desirable to receive digital audio data with the sta120 and retransmit it with the sta020d. in this case, channel status, user and validity information must pass through unaltered. for studio environments, aes re commends that signal timing synchron ization be maintai ned throughout the studio. frame synchronization of digital audio signal s input to and output from a piece of equipment must be within 5%. the transparent mode of the sta020d is selected by setting trnpt, pin 24, high. in this mode, the cbl pin becomes an input, allowing direct connection of the outputs of the sta120 to the inputs of the sta020d as shown in figure 18. the transmitter and receiver are synchronize d by the fsync signal. cbl specifies the start of a new channel status block boundry, allowing the transmit block structure to be slaved to the block structure of the receiver. in the transparent mode, c, u and v are now transmitted with the current audio sample as shown in figure 5 (trnpt high) and the dedicated channel status pins are ignored. when fsync is a word clock (format 2), cbl is samp led when left c, u, v are sampled. when fsync is left/right, cbl is sampled when left c, u, v are sampled. the channel status block boundry is reset when cbl transitions from low to high (based on tw o successive samples of cb l). mck for the sta020d is normally expected to be 128 times the sample frequency, in the trasparent mode mck must be 256 fs. professional mode setting pro low places the sta020d in professional mode as shown in figure 6. in professional mode, channel status bit 0 is transmitted as a one and bits 1, 2, 3, 4, 6, 7 and 9 can be controlled via dedicated pins. the pins are actually the inverse of the identified bit. for example, tying the c1 pin low places a one in channel status bit 1. as shown in the application note, overview of aes/ebu digital audi o interface data structures, c1 indicates audio/non-audio; c6 and c7 determine the sample frequency and c9 allows the encoded channel mode to be stereophonic. em1 and em0 determine emphasis and encode c2 , c3 , c4 as shown in table 2. the dedicated channel status pins are read at the appropriate time and are logically or?ed with data input on the channel status port, c. in transparent mode, these dedicated channel status pins are ignored and channel status bits are input at the c pin. consumer mode setting pro high places the sta020d in consumer mode which redefines the pins as shown in figure 7. in consumer mode, channel status bit 0 is transmitted as a zero and channel status bits 2, 3, 8, 9, 15, 24 and 25 are controlled via dedicated pins. the pins are actually the inverse of the bit so if pin c2 is tied high, channel status bit 2 will be transmitted as a zero. also, fc0 and fc1 are encoded versions of channel status bits 24 and 25, which define the sample frequency. when fc0 and fc1 are both high, the part is placed in a cd submode which activates the cd subcode port. this submode is described in detail in the next section. table 3 describes the encoding of c24 and c25 through the fc1 and fc0 pins. according to aes/ebu standards, c2 is copy prohibit/permit. c3 specifies pre-emphasis, c8 and c9 define the category code and c15 identifies the generation status of the transmitted material (i.e. first generation, second generation). table 2. emphasis encoding em1 em0 c2 c3 c4 00111 01110 10100 11000 obsolete product(s) - obsolete product(s)
sta020 10/14 table 3. sample frequency encoding figure 5. transparent mode interface. figure 6. block diagram - professional mode fc1 fc0 c24 c25 comments 0 0 0 0 44.1khz 0 1 0 1 48khz 1 0 1 1 32khz 1 1 0 0 44.1khz, cd mode mck cbl c u v fsync data processing rxp rxn sck sta120 sta020 txn txp trnpt v+ d97au605 sdata serial port logic registers m0 m1 m2 23 22 21 audio aux c bits u bits validity preamble parity sdata 8 sck 6 fsync 7 c 10 u 11 v 9 mux biphase mark encoder line driver timing 2141334112 15 5 16 17 20 em0 em1 c1 c6 c7 c9 cbl mck pro rst txn txp d97au607b trnpt 24 mux crc obsolete product(s) - obsolete product(s)
11/14 sta020 figure 7. block diagram - consumer mode serial port logic registers m0 m1 m2 23 22 21 audio aux c bits u bits validity preamble parity sdata 8 sck 6 fsync 7 c 10 u 11 v 9 mux biphase mark encoder line driver timing 2 +3.3v 3 24 4 1 13 14 12 15 5 16 17 20 fc0 fc1 c2 c3 c8 c9 c15 cbl mck pro rst txn txp d97au606a mux obsolete product(s) - obsolete product(s)
sta020 12/14 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so24 0070769 c weight: 0.60gr obsolete product(s) - obsolete product(s)
13/14 sta020 revision history date revision changes 14-oct-2002 5 technical migration from st-press to edocs 26-apr-2010 6 major revision for revalidation process obsolete product(s) - obsolete product(s)
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